Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
FIG. 1 is a simplified illustration of an exemplary FPGA. The FPGA of FIG. 1 includes an array of configurable logic blocks (LBs 101a–101i) and programmable input/output blocks (I/Os 102a–102d). The LBs and I/O blocks are interconnected by a programmable interconnect structure that includes a large number of interconnect lines 103 interconnected by programmable interconnect points (PIPs 104, shown as small circles in FIG. 1). PIPs are often coupled into groups (e.g., group 105) that implement multiplexer circuits selecting one of several interconnect lines to provide a signal to a destination interconnect line or logic block. Some FPGAs also include additional logic blocks with special purposes (not shown), e.g., DLLS, RAM, and so forth.
One programmable element commonly found in FPGA logic blocks is the lookup table, or LUT. A LUT is a memory array (e.g., a 16×1 array) that is addressable by a number of input signals (e.g., four input signals). By programming predetermined values into the memory array, the LUT can implement any function of the input variables. While 4-input functions are common in user circuits, it can also be desirable to provide simple and fast implementations of larger and/or smaller logic functions.
FPGAs have been manufactured that allow a combination of LUTs to be grouped together using dedicated logic, where the grouped LUTs can be used to implement larger functions. For example, the XC3000™ family of FPGAs from Xilinx, Inc. offers the capability of combining two 4-input LUTs to implement a 5-input function generator, as shown and described on pages 2–110 and 2–111 of “The Programmable Logic Data Book 1994”, published in 1994 and available from Xilinx, Inc., 2100 Logic Dr., San Jose, Calif. 95124. (These pages are hereby incorporated herein by reference.)
In U.S. Pat. No. 6,400,180 B2, Wittig et al. utilize a different approach to the issue of providing versatility in function generator logic, by providing a single function generator circuit that can be optionally divided to function as two smaller LUTs. However, the two LUTs are not independent of each other, in that some of the input signals are shared between the two LUTs. (U.S. Pat. No. 6,400,180 B2, entitled “Configurable Lookup Table for Programmable Logic Devices” and issued Jun. 4, 2002, is hereby incorporated herein by reference, in its entirety.)
In the aforementioned patent, Wittig et al. describe a “versatile implementation module” (VIM) that includes a lookup table configurable in two different modes (see FIG. 3 of Wittig et al.). The VIM is configurable as two 5-input lookup tables (in 5-LUT and 6-LUT mode) or as one 8-input product term generator. In 5-LUT and 6-LUT mode, two of the input signals (g3 and g4) are shared between the two LUTs. Therefore, the described structure imposes some limitations on the user logic functions that can be combined in a single VIM.
To increase the flexibility of combining small user functions into a single LUT circuit, it is desirable to provide a LUT circuit for a PLD that allows the LUT circuit to be used as a single large LUT, or as two or more smaller LUTs with independent input signals.